| PSW | F | UF | 0x97 | User Flag - Available to be used freely. |
| PSW | E | UE | 0x96 | User Flag - Available to be used freely. |
| PSW | D | UD | 0x95 | User Flag - Available to be used freely. |
| PSW | C | UC | 0x94 | User Flag - Available to be used freely. |
| PSW | B | UB | 0x93 | User Flag - Available to be used freely. |
| PSW | A | UA | 0x92 | User Flag - Available to be used freely. |
| PSW | 9 | U9 | 0x91 | User Flag - Available to be used freely. |
| PSW | 8 | U8 | 0x90 | User Flag - Available to be used freely. |
| PSW | 7 | U7 | 0x87 | User Flag - Available to be used freely. |
| PSW | 6 | U6 | 0x86 | User Flag - Available to be used freely. |
| PSW | 5 | U5 | 0x85 | User Flag - Available to be used freely. |
| PSW | 4 | U4 | 0x84 | User Flag - Available to be used freely. |
| PSW | 3 | U3 | 0x83 | User Flag - Available to be used freely. |
| PSW | 2 | U2 | 0x82 | User Flag - Available to be used freely. |
| PSW | 1 | OV | 0x81 | Overflow Flag - This bit is set when a mathematical operation returns a value outside the signed int range (-32,768 to +32,767). |
| PSW | 0 | C | 0x80 | Carry Flag - This bit is set when a carry bit is left by a mathematical operation. |
| TCON | F | TF3 | 0x8B | Timer 3 Overflow - This bit is set by the microcontroller when Timer 3 overflows. |
| TCON | E | TR3 | 0x8A | Timer 3 Run - When this bit is set Timer 3 is turned on. When this bit is clear Timer 3 is off. |
| TCON | D | GATE3 | 0xEF | Gate 3 Timer - When this bit is set Timer 3 will only run when XG3 is high, otherwise it will run regardless of the state of XG3. |
| TCON | C | CT3 | 0xEE | Counter/Timer 3 Select - When this bit is set Timer 3 will count events on XI3, otherwise it will be incremented every computational cycle. |
| TCON | B | TF2 | 0x89 | Timer 2 Overflow - This bit is set by the microcontroller when Timer 2 overflows. |
| TCON | A | TR2 | 0x88 | Timer 2 Run - When this bit is set Timer 2 is turned on. When this bit is clear Timer 2 is off. |
| TCON | 9 | GATE2 | 0xED | Gate 2 Timer - When this bit is set Timer 2 will only run when XG2 is high, otherwise it will run regardless of the state of XG2. |
| TCON | 8 | CT2 | 0xEC | Counter/Timer 2 Select - When this bit is set Timer 2 will count events on XI2, otherwise it will be incremented every computational cycle. |
| TCON | 7 | TF1 | 0x8F | Timer 1 Overflow - This bit is set by the microcontroller when Timer 1 overflows. |
| TCON | 6 | TR1 | 0x8E | Timer 1 Run - When this bit is set Timer 1 is turned on. When this bit is clear Timer 1 is off. |
| TCON | 5 | GATE1 | 0xEB | Gate 1 Timer - When this bit is set Timer 1 will only run when XG1 is high, otherwise it will run regardless of the state of XG1. |
| TCON | 4 | CT1 | 0xEA | Counter/Timer 1 Select - When this bit is set Timer 1 will count events on XI1, otherwise it will be incremented every computational cycle. |
| TCON | 3 | TF0 | 0x8D | Timer 0 Overflow - This bit is set by the microcontroller when Timer 0 overflows. |
| TCON | 2 | TR0 | 0x8C | Timer 0 Run - When this bit is set Timer 0 is turned on. When this bit is clear Timer 0 is off. |
| TCON | 1 | GATE0 | 0xE9 | Gate 0 Timer - When this bit is set Timer 0 will only run when XG0 is high, otherwise it will run regardless of the state of XG0. |
| TCON | 0 | CT0 | 0xE8 | Counter/Timer 0 Select - When this bit is set Timer 0 will count events on XI0, otherwise it will be incremented every computational cycle. |
| XCON | C–F | | | Undefined |
| XCON | B | XG3 | 0xCF | Gate 3 Active - This bit is set by the microcontroller when External Gate 3 is receiving signal. |
| XCON | A | XG2 | 0xCE | Gate 2 Active - This bit is set by the microcontroller when External Gate 2 is receiving signal. |
| XCON | 9 | XG1 | 0xCD | Gate 1 Active - This bit is set by the microcontroller when External Gate 1 is receiving signal. |
| XCON | 8 | XG0 | 0xCC | Gate 0 Active - This bit is set by the microcontroller when External Gate 0 is receiving signal. |
| XCON | 7 | XI7 | 0x9F | Port 7 Received - This bit is set by the microcontroller when External Port 7 has received data. |
| XCON | 6 | XI6 | 0x9E | Port 6 Received - This bit is set by the microcontroller when External Port 6 has received data. |
| XCON | 5 | XI5 | 0x9D | Port 5 Received - This bit is set by the microcontroller when External Port 5 has received data. |
| XCON | 4 | XI4 | 0x9C | Port 4 Received - This bit is set by the microcontroller when External Port 4 has received data. |
| XCON | 3 | XI3 | 0x9B | Port 3 Received - This bit is set by the microcontroller when External Port 3 has received data. |
| XCON | 2 | XI2 | 0x9A | Port 2 Received - This bit is set by the microcontroller when External Port 2 has received data. |
| XCON | 1 | XI1 | 0x99 | Port 1 Received - This bit is set by the microcontroller when External Port 1 has received data. |
| XCON | 0 | XI0 | 0x98 | Port 0 Received - This bit is set by the microcontroller when External Port 0 has received data. |
| IE | F | EA | 0xAF | Enable All Interrupts - When this bit is not set (bit is 0), all interrupts are disabled regardless of the corresponding lower bit settings. |
| IE | C–E | | | Undefined |
| IE | B | EP7 | 0xDC | Enable Port 7 Interrupt - When this bit is set, interrupts will be caught for External Port 7 receiving data (XI7). |
| IE | A | EP6 | 0xDB | Enable Port 6 Interrupt - When this bit is set, interrupts will be caught for External Port 6 receiving data (XI6). |
| IE | 9 | EP5 | 0xDA | Enable Port 5 Interrupt - When this bit is set, interrupts will be caught for External Port 5 receiving data (XI5). |
| IE | 8 | EP4 | 0xD9 | Enable Port 4 Interrupt - When this bit is set, interrupts will be caught for External Port 4 receiving data (XI4). |
| IE | 7 | ET3 | 0xD8 | Enable Timer 3 Interrupt - When this bit is set, interrupts will be caught for Timer 3 overflowing (TF3). |
| IE | 6 | EP3 | 0xAE | Enable Port 3 Interrupt - When this bit is set, interrupts will be caught for External Port 3 receiving data (XI3). |
| IE | 5 | ET2 | 0xAD | Enable Timer 2 Interrupt - When this bit is set, interrupts will be caught for Timer 2 overflowing (TF2). |
| IE | 4 | EP2 | 0xAC | Enable Port 2 Interrupt - When this bit is set, interrupts will be caught for External Port 2 receiving data (XI2). |
| IE | 3 | ET1 | 0xAB | Enable Timer 1 Interrupt - When this bit is set, interrupts will be caught for Timer 1 overflowing (TF1). |
| IE | 2 | EP1 | 0xAA | Enable Port 1 Interrupt - When this bit is set, interrupts will be caught for External Port 1 receiving data (XI1). |
| IE | 1 | ET0 | 0xA9 | Enable Timer 0 Interrupt - When this bit is set, interrupts will be caught for Timer 0 overflowing (TF0). |
| IE | 0 | EP0 | 0xA8 | Enable Port 0 Interrupt - When this bit is set, interrupts will be caught for External Port 0 receiving data (XI0). |
| IP | C–F | | | Undefined |
| IP | B | PP7 | 0xCB | Port 7 Interrupt Priority - When this bit is set, External Port 7 interrupts will have high priority. |
| IP | A | PP6 | 0xCA | Port 6 Interrupt Priority - When this bit is set, External Port 6 interrupts will have high priority. |
| IP | 9 | PP5 | 0xC9 | Port 5 Interrupt Priority - When this bit is set, External Port 5 interrupts will have high priority. |
| IP | 8 | PP4 | 0xC8 | Port 4 Interrupt Priority - When this bit is set, External Port 4 interrupts will have high priority. |
| IP | 7 | PT3 | 0xBF | Timer 3 Interrupt Priority - When this bit is set, Timer 3 interrupts will have high priority. |
| IP | 6 | PP3 | 0xBE | Port 3 Interrupt Priority - When this bit is set, External Port 3 interrupts will have high priority. |
| IP | 5 | PT2 | 0xBD | Timer 2 Interrupt Priority - When this bit is set, Timer 2 interrupts will have high priority. |
| IP | 4 | PP2 | 0xBC | Port 2 Interrupt Priority - When this bit is set, External Port 2 interrupts will have high priority. |
| IP | 3 | PT1 | 0xBB | Timer 1 Interrupt Priority - When this bit is set, Timer 1 interrupts will have high priority. |
| IP | 2 | PP1 | 0xBA | Port 1 Interrupt Priority - When this bit is set, External Port 1 interrupts will have high priority. |
| IP | 1 | PT0 | 0xB9 | Timer 0 Interrupt Priority - When this bit is set, Timer 0 interrupts will have high priority. |
| IP | 0 | PP0 | 0xB8 | Port 0 Interrupt Priority - When this bit is set, External Port 0 interrupts will have high priority. |